During the past fifty years, the electronics and computing industries have steadily increased the speed of digital computing devices and made remarkable progress in reducing the size and speed of computing device internal components, such as logic circuits and memory. Internal components are typically integrated on a single substrate and referred to as a “chip or “integrated circuit” (“IC”). Networks of electrical interconnections, referred to as “global interconnects,” link these internal components, such as interconnections that link logic and memory. Global interconnects are composed of signal lines that transmit data between internal components and distribute power and clock signals to internal components.
Clock signals are electrical signals that cycle between a high electrical state and a low electrical state at a specific rate. Typical ICs use a clock signal to synchronize the operation of different internal components. Internal components receiving a clock signal may become active on either the rising edge or the falling edge of each cycle of the clock signal. The rate at which the clock signal cycles between a high electronic state and a low electronic state is called the “clock rate.” The clock rate, measured in cycles per second (“Hz”), is the rate at which an IC performs its most basic operations, such as transmitting data between internal components. As the clock rate is increased, the internal components generally transmit data and carry out instructions more quickly.
In order to decrease the amount of time needed to transmit data between internal components, ICs are typically designed so that the distances between internal components exchanging large amounts of data are shorter than the distances between internal components exchanging small amounts of data. However, a clock signal is typically distributed from a single clock signal source to each internal component over a single global interconnect. As a result, clock signals traverse the longest signal line distances, and operate at the highest speeds of any signal, either control or data, transmitted within the IC. The clock signal source may include a crystal, such as a quartz crystal, that generates the clock signal by oscillating at a predictable rate within the megahertz (“MHz”) or gigahertz (“GHz”) frequency ranges. For example, crystal-based clock rates as high as 3 GHz have been achieved.
FIGS. 1A-1B illustrate an exemplary global interconnect that distributes a clock signal to numerous internal components of a hypothetical IC. In FIG. 1A, IC 101 is composed of a number of internal components identified by rectangles. For example, rectangles 102-104 represent random access memory and rectangle 105 represents a central processing unit. A clock signal generated by clock signal source 106 is distributed to the internal components via a global interconnect comprising a network of signal lines, such as signal line 107. FIG. 1B is a plot of an exemplary clock signal distributed by clock signal source 106. The internal components of IC 101 may each be activated on a rising edge of a clock cycle, such as clock cycle edge 108. Because the global interconnect employs signal lines located between the internal components, internal components located farthest from clock signal source 106, such as internal component 102, may receive a clock cycle later than internal components located closer to clock signal source 106. As a result, the internal components do not all receive the same clock signal at the same time. For example, stippled internal component 105 may receive clock cycle 110 at about the same time blank internal component 109 receives clock cycle 111,
In spite of efforts to improve the design of IC architectures and the design of global interconnects to distribute clock signals, the percentage of a chip that can be reached within a few clock cycles has continued to decrease as the number of internal components integrated on a single chip has increased, and clock frequencies have increased. In addition, the global interconnects employed are rapidly approaching fundamental physical limits with respect to the information carrying capacity of metal wires. In general, as IC internal components and electronic interconnects shrink from microscale dimensions to nanoscale dimensions, intrinsic capacitance of the electronic interconnections greatly increases and exceeds that of the nanoscale internal components. As a result, the information carrying capacity of each wire in a global interconnect decreases, and closely spaced wires cannot be accessed at high speeds without creating interference, including inducing currents in adjacent wires. Thus, even though the internal component density can be increased by decreasing the size of IC internal components, the number of transistors that can be reached in one clock cycle of a clock signal may significantly decrease. Manufacturers, designers, and users of computing devices have recognized a need for new global interconnects that can uniformly distribute clock signals and can accommodate the ever increasing demand for higher clock rates.